Clock control register
| DIV_SEL | Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is ‘63’ and TYPE_SEL is ‘3’ (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one ‘clk_peri’ cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is ‘63’ and TYPE_SEL is ‘3’) for a transition time that is larger than the smaller of the two divider periods. |
| TYPE_SEL | Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. |